1. Field of the Invention
The present invention relates to a display apparatus, and more particularly, to a shift register circuit possessed by a scanning signal line driver circuit such as liquid-crystal display (LCD).
2. Description of the Related Art
Hitherto, thin-film transistors (TFTs) using polysilicon (p-Si) were the major TFTs used in small-size LCDs which are mounted on portable information processing devices such as cellular phones. In recent years, however, TFT-LCDs using amorphous silicon (a-Si) which is non-crystalline silicon have been developed in order to decrease a mounting cost. Moreover, in order to reduce the area of a non-display portion in the a-Si TFT-LCD, there is proposed a structure having shift registers in which a shift register circuit for scanning a gate line is integrated and mounted at the same time as TFTs of a pixel unit.
A shift register circuit using a-Si TFTs is disclosed in JP 2005-293817 A, for example. The shift register circuit has a plurality of stages, and each stage includes: a pull-up transistor controlled by a first node to supply a first clock signal to an output line; a pull-down transistor controlled by a second node to supply a first driving voltage to the output line; a controller for controlling the first and second nodes so as to have opposite potential levels; and a compensating capacitor connected between the first node and an input line of a second clock signal so as to compensate for a fluctuation amount caused by parasitic capacitors among the first node, the first clock signal, and the pull-up transistor.
FIG. 18 shows a part of a detailed circuit of one stage of a plurality of stages which is subordinately connected in a shift register according to the related art. A gate output operation according to the related art will be described for the following three steps with reference to FIG. 18.
First, in the first step, a high voltage of a start pulse (VST) is supplied in synchronization with a voltage of a clock signal (/C1). The high voltage of the clock signal (/C1) turns on a transistor (T1), and the high voltage of the start pulse (VST) is supplied to a node Q, namely the node Q is precharged. The precharged high voltage at the node Q turns on a transistor (T5), and the transistor (T5) supplies a low voltage of a clock signal (C1) to an output line. At that time, the high voltage of the second clock signal (/C1) also turns on a transistor (T2), and a high-level voltage (VDD) is supplied to a node QB. The high-level voltage (VDD) supplied to the node QB also turns on a transistor (T6), and the transistor (T6) outputs a low-level voltage (VSS). Here, the high-level voltage (VDD) and the low-level voltage (VSS) always maintain a constant voltage. In this way, during the first period A, the stage outputs a low-state output signal (OUT) from the output line.
In the second step, a low voltage of the clock signal (/C1) turns off the transistor (T1) and the node Q floats in the high state. Thus, the transistor (T5) maintains the on state. At that time, the high voltage is supplied to the clock signal (C1), whereby the floating node Q is bootstrapped by an effect of a parasitic capacitor (CGS) which is formed between a gate electrode and a source electrode of the transistor (T5). Accordingly, the voltage at the node Q rises further, the transistor (T5) is completely turned on, and the high voltage of the clock signal (C1) is supplied quickly to the output line. In addition, the transistor (T4) is turned on by the voltage of the node Q floating in the high state, and the transistor (T3) is turned on by the high-state clock signal (C1). Thus, the low-level voltage (VSS) is supplied to the node QB, and the transistor (T6) is turned off. In this way, during the second period B, the stage outputs a high-state output signal (OUT) from the output line.
In the third step, the high voltage of the clock signal (/C1) turns on the transistor (T1) and the low voltage of the start pulse (VST) is supplied to the node Q. Thus, the transistor (T5) is turned off. At that time, the high voltage of the clock signal (/C1) turns on the transistor (T2), and the high-level voltage (VDD) is supplied to the node QB. Thus, the transistor (T6) is turned on, and the low-level voltage (VSS) is output to the output line. At that time, the transistor (T3) is turned off by the low voltage of the clock signal (C1), and the transistor (T4) is turned off by the low voltage of the node Q. Thus, the high-level voltage (VDD) is maintained at the node QB. In this way, during the third period C, the stage outputs a low-state output signal (OUT) from the output line.
Through the operation steps, the gate output signal is output. However, in the second step, since the high voltage raised by the bootstrapping is applied to the gate of the transistor T4, a shift of the threshold voltage of the transistor T4 is accelerated in a direction of increasing the threshold voltage.
In particular, when the shift of the threshold voltage of the transistor T4 is accelerated in the direction of increasing the threshold voltage due to the threshold voltage shifting characteristics, there is a problem in that the driving capability to supply the low-level voltage (VSS) to the node QB decreases, and the node QB floats in the high level. When the node QB is in the high state, the transistor (T6) is turned on. Thus, the output signal (OUT) which is originally in the high state is pulled down to the low state. As a result, there is a problem in that the output signal (OUT) disappears, thus causing display errors.